A Novel Power Efficient On-chip Test Generation Scheme for Core Based System-on-chip (soc)
نویسندگان
چکیده
In this paper, a modified programmable twisted ring counter (MPTRC) based on-chip test generation scheme is proposed. It is used as built-in-self-test (BIST) pattern generator for high performance circuits with simple test control. This method is used to achieve low power and reduced test time for digital circuits. The MPTRC module is designed with Cadence NClaunch platform using Verilog HDL and synthesis done by using Cadence RTL compiler with 0.18μm technology. The simulation results show about 13.46% power reduction compared with conventional programmable twisted ring counter (PTRC) based design.
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تاریخ انتشار 2015